2020-05-19 12:02:15 +00:00
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# nand2tetris
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2020-05-19 14:06:41 +00:00
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Working my way through the [Nand to Tetris Course](https://www.nand2tetris.org/)
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2020-05-19 12:42:52 +00:00
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- Download the latest `nand2tetris.zip` from the book website, and overwrite everything in the `projects` and `tools` directory.
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- Remember to run `chmod +X tools/*.sh` if you're on \*nix.
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2020-05-19 14:03:19 +00:00
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## [Project 1: Boolean Logic](https://www.nand2tetris.org/project01)
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Build order as per the website. Cost for each gate in NAND in brackets.
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- [x] `Nand` (primitive)
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- [x] `Not` (1)
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- [x] `Or` (3)
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2020-05-19 16:52:53 +00:00
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- [x] `Xor` (6, Can be improved)
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2020-05-19 14:03:19 +00:00
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- [x] `And` (2)
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2020-05-19 16:52:53 +00:00
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- [x] `Mux` (8, Took me ages. Can be improved)
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2020-05-19 14:03:19 +00:00
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- [x] `DMux` (5, Super Fun)
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- [x] `Not16` (16)
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- [x] `And16` (32)
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- [x] `Or16` (48)
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2020-05-19 16:52:53 +00:00
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- [x] `Mux16` (113)
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2020-05-19 17:22:09 +00:00
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- [x] `Or8Way` (21)
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2020-05-19 20:32:46 +00:00
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- [x] `Mux4Way16` (339)
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- [x] `Mux8Way16` (791)
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2020-05-20 09:07:46 +00:00
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- [x] `DMux4Way` (37, Fun)
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2020-05-20 09:16:51 +00:00
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- [x] `DMux8Way` (101)
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2020-05-20 11:18:14 +00:00
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## [Project 2: Boolean Arithmetic](https://www.nand2tetris.org/project02)
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2020-05-20 20:29:59 +00:00
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CHIPs/Gates used in brackets
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- [x] `HalfAdder` (Xor+And)
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- [x] `FullAdder` (2 HalfAdder, 1 Or)
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- [x] `Add16` (1 HalfAdder, 15 FullAdder)
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- [x] `Inc16` (1 Add16)
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- [x] `ALU` (6 Mux16, 3 Not16, 1 Add16, 1 And16, 2 Or8Way, 2 Or, 1 Not)
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2020-05-20 13:19:00 +00:00
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## [Project 3: Memory](https://www.nand2tetris.org/project03)
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2020-05-20 20:29:59 +00:00
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Make sure you read through the [Hardware Simulator Tutorial][s] to understand the clock in the simulator.
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2020-05-20 13:19:00 +00:00
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2020-05-20 19:36:50 +00:00
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- [x] `DFF` (primitive)
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- [x] `Bit` (1 Mux, 1DFF)
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- [x] `Register` (16 Bits)
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2020-05-28 09:34:07 +00:00
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- [x] `RAM8` (8 Registers, 1 DMux8Way, 1 Mux8Way16) = 8 registers
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- [x] `RAM64` (8 RAM8, 1 DMux8Way, 1 Mux8Way16) = 64 registers
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- [x] `RAM512` (8 RAM64, 1 DMux8Way, 1 Mux8Way16) = 512 registers
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- [x] `RAM4K` (8 RAM512, 1 DMux8Way, 1 Mux8Way16) = 4096 registers
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- [x] `RAM16K` (4 RAM4K, 1 DMux4Way, 1 Mux4Way16) = 16384 registers
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2020-05-20 19:36:50 +00:00
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- [x] `PC` (1 Register, 1 Inc16, 1 Or8Way, 1 Mux8Way16)
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2020-05-20 20:29:59 +00:00
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[s]: https://b1391bd6-da3d-477d-8c01-38cdf774495a.filesusr.com/ugd/44046b_bfd91435260748439493a60a8044ade6.pdf
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2020-05-28 09:34:07 +00:00
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## [Project 3: Machine Language Programming](https://www.nand2tetris.org/project03)
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2020-05-28 11:18:24 +00:00
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Counting number of instructions by `wc -l $file.hack`
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2020-05-28 09:34:07 +00:00
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- [x] Mult (18)
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2020-05-28 11:18:24 +00:00
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- [x] Fill (98)
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