Fixes RAM16K. I was using too many registers and the addressing was

wrong
pull/1/head
Nemo 3 years ago
parent 37c0f41a4a
commit 90526cc036
  1. 17
      README.md
  2. 21
      projects/03/b/RAM16K.hdl

@ -43,11 +43,18 @@ Make sure you read through the [Hardware Simulator Tutorial][s] to understand th
- [x] `DFF` (primitive)
- [x] `Bit` (1 Mux, 1DFF)
- [x] `Register` (16 Bits)
- [x] `RAM8` (8 Registers, 1 DMux8Way, 1 Mux8Way16)
- [x] `RAM64` (8 RAM8, 1 DMux8Way, 1 Mux8Way16)
- [x] `RAM512` (8 RAM64, 1 DMux8Way, 1 Mux8Way16)
- [x] `RAM4K` (8 RAM512, 1 DMux8Way, 1 Mux8Way16)
- [x] `RAM16K` (8 RAM4K, 1 DMux8Way, 1 Mux8Way16)
- [x] `RAM8` (8 Registers, 1 DMux8Way, 1 Mux8Way16) = 8 registers
- [x] `RAM64` (8 RAM8, 1 DMux8Way, 1 Mux8Way16) = 64 registers
- [x] `RAM512` (8 RAM64, 1 DMux8Way, 1 Mux8Way16) = 512 registers
- [x] `RAM4K` (8 RAM512, 1 DMux8Way, 1 Mux8Way16) = 4096 registers
- [x] `RAM16K` (4 RAM4K, 1 DMux4Way, 1 Mux4Way16) = 16384 registers
- [x] `PC` (1 Register, 1 Inc16, 1 Or8Way, 1 Mux8Way16)
[s]: https://b1391bd6-da3d-477d-8c01-38cdf774495a.filesusr.com/ugd/44046b_bfd91435260748439493a60a8044ade6.pdf
## [Project 3: Machine Language Programming](https://www.nand2tetris.org/project03)
Counting number of instructions by `wc -l file.hack`
- [x] Mult (18)
- [ ] Fill

@ -16,35 +16,24 @@ CHIP RAM16K {
PARTS:
// The MSB of the address picks which RAM4K module is being picked
DMux8Way(in=load, sel=address[11..13],
DMux4Way(in=load, sel=address[12..13],
a=load1,
b=load2,
c=load3,
d=load4,
e=load5,
f=load6,
g=load7,
h=load8);
d=load4
);
// We use the LSB of the address to pick the register inside the RAM4K
RAM4K(in=in, load=load1, address=address[0..11], out=out1);
RAM4K(in=in, load=load2, address=address[0..11], out=out2);
RAM4K(in=in, load=load3, address=address[0..11], out=out3);
RAM4K(in=in, load=load4, address=address[0..11], out=out4);
RAM4K(in=in, load=load5, address=address[0..11], out=out5);
RAM4K(in=in, load=load6, address=address[0..11], out=out6);
RAM4K(in=in, load=load7, address=address[0..11], out=out7);
RAM4K(in=in, load=load8, address=address[0..11], out=out8);
// MSB
Mux8Way16(
Mux4Way16(
a=out1,
b=out2,
c=out3,
d=out4,
e=out5,
f=out6,
g=out7,
h=out8,
sel=address[11..13], out=out);
sel=address[12..13], out=out);
}

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