[03] Program Counter
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README.md
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README.md
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@ -39,12 +39,13 @@ Build order as per the website. Cost for each gate in NAND in brackets.
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Make sure you read through the [Hardware Simulator Tutorial](https://b1391bd6-da3d-477d-8c01-38cdf774495a.filesusr.com/ugd/44046b_bfd91435260748439493a60a8044ade6.pdf) to understand the clock in the simulator.
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- [x] DFF (primitive)
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- [x] Bit (1 Mux, 1DFF)
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- [x] Register (16 Bits)
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- [x] RAM8 (8 Registers, 1 DMux8Way, 1 Mux8Way16)
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- [x] RAM64 (8 RAM8, 1 DMux8Way, 1 Mux8Way16)
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- [x] RAM512 (8 RAM64, 1 DMux8Way, 1 Mux8Way16)
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- [x] RAM4K (8 RAM512, 1 DMux8Way, 1 Mux8Way16)
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- [x] RAM16K (8 RAM4K, 1 DMux8Way, 1 Mux8Way16)
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- [ ] PC
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- [x] `DFF` (primitive)
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- [x] `Bit` (1 Mux, 1DFF)
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- [x] `Register` (16 Bits)
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- [x] `RAM8` (8 Registers, 1 DMux8Way, 1 Mux8Way16)
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- [x] `RAM64` (8 RAM8, 1 DMux8Way, 1 Mux8Way16)
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- [x] `RAM512` (8 RAM64, 1 DMux8Way, 1 Mux8Way16)
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- [x] `RAM4K` (8 RAM512, 1 DMux8Way, 1 Mux8Way16)
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- [x] `RAM16K` (8 RAM4K, 1 DMux8Way, 1 Mux8Way16)
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- [x] `PC` (1 Register, 1 Inc16, 1 Or8Way, 1 Mux8Way16)
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@ -16,5 +16,64 @@ CHIP PC {
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OUT out[16];
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PARTS:
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// Put your code here:
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// We use this IF inc=1
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Inc16(in=registerout, out=incrementedoutput);
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// We setup a Mux using the 3 bits as the inputs
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// for the Mux. Higher priority uses MSB
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// [ reset | load | inc ]
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// [ sel[2]|sel[1]|sel[0] ]
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// DO NOTHING For this case
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// a if sel == 000
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// INC for this case
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// b if sel == 001
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// LOAD for the below 2 cases
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// c if sel == 010
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// d if sel == 011
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// RESET for all 4 cases below
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// e if sel == 100
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// f if sel == 101
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// g if sel == 110
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// h if sel == 111
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// a-d: we reset
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// e-f: we load
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// g: we increment
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// h: do nothing
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// We don't have a Or3Way, so using this for now
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// This sets pleaseupdate to true if either of the
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// reset|load|inc operations is in call
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Or8Way(
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in[0]=inc,
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in[1]=load,
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in[2]=reset,
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in[3]=false,
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in[4]=false,
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in[5]=false,
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in[6]=false,
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in[7]=false,
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out=pleaseupdate);
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Mux8Way16(
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// While this is false it doesn't matter
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// since pleaseupdate = 0 in this case
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// and register won't reset
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a=false,
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// INCREMENT for this case
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b=incrementedoutput,
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// LOAD for these 2 cases
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c=in,
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d=in,
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// please pass 0 as input to the register
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// RESET
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e=false,
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f=false,
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g=false,
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h=false,
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sel[2]=reset,
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sel[1]=load,
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sel[0]=inc,
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out=registerinput);
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Register(in=registerinput, load=pleaseupdate, out=registerout, out=out);
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}
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@ -0,0 +1,31 @@
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| time | in |reset|load | inc | out |
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| 0+ | 0 | 0 | 0 | 0 | 0 |
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| 1 | 0 | 0 | 0 | 0 | 0 |
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| 1+ | 0 | 0 | 0 | 1 | 0 |
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| 2 | 0 | 0 | 0 | 1 | 1 |
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| 2+ | -32123 | 0 | 0 | 1 | 1 |
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| 3 | -32123 | 0 | 0 | 1 | 2 |
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| 3+ | -32123 | 0 | 1 | 1 | 2 |
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| 4 | -32123 | 0 | 1 | 1 | -32123 |
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| 4+ | -32123 | 0 | 0 | 1 | -32123 |
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| 5 | -32123 | 0 | 0 | 1 | -32122 |
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| 5+ | -32123 | 0 | 0 | 1 | -32122 |
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| 6 | -32123 | 0 | 0 | 1 | -32121 |
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| 6+ | 12345 | 0 | 1 | 0 | -32121 |
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| 7 | 12345 | 0 | 1 | 0 | 12345 |
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| 7+ | 12345 | 1 | 1 | 0 | 12345 |
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| 8 | 12345 | 1 | 1 | 0 | 0 |
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| 8+ | 12345 | 0 | 1 | 1 | 0 |
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| 9 | 12345 | 0 | 1 | 1 | 12345 |
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| 9+ | 12345 | 1 | 1 | 1 | 12345 |
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| 10 | 12345 | 1 | 1 | 1 | 0 |
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| 10+ | 12345 | 0 | 0 | 1 | 0 |
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| 11 | 12345 | 0 | 0 | 1 | 1 |
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| 11+ | 12345 | 1 | 0 | 1 | 1 |
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| 12 | 12345 | 1 | 0 | 1 | 0 |
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| 12+ | 0 | 0 | 1 | 1 | 0 |
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| 13 | 0 | 0 | 1 | 1 | 0 |
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| 13+ | 0 | 0 | 0 | 1 | 0 |
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| 14 | 0 | 0 | 0 | 1 | 1 |
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| 14+ | 22222 | 1 | 0 | 0 | 1 |
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| 15 | 22222 | 1 | 0 | 0 | 0 |
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