diff --git a/README.md b/README.md
index a4d6324..7bb4beb 100644
--- a/README.md
+++ b/README.md
@@ -39,12 +39,13 @@ Build order as per the website. Cost for each gate in NAND in brackets.
 
 Make sure you read through the [Hardware Simulator Tutorial](https://b1391bd6-da3d-477d-8c01-38cdf774495a.filesusr.com/ugd/44046b_bfd91435260748439493a60a8044ade6.pdf) to understand the clock in the simulator.
 
-- [x] DFF (primitive)
-- [x] Bit (1 Mux, 1DFF)
-- [x] Register (16 Bits)
-- [x] RAM8 (8 Registers, 1 DMux8Way, 1 Mux8Way16)
-- [x] RAM64 (8 RAM8, 1 DMux8Way, 1 Mux8Way16)
-- [x] RAM512 (8 RAM64, 1 DMux8Way, 1 Mux8Way16)
-- [x] RAM4K (8 RAM512, 1 DMux8Way, 1 Mux8Way16)
-- [x] RAM16K (8 RAM4K, 1 DMux8Way, 1 Mux8Way16)
-- [ ] PC
+- [x] `DFF` (primitive)
+- [x] `Bit` (1 Mux, 1DFF)
+- [x] `Register` (16 Bits)
+- [x] `RAM8` (8 Registers, 1 DMux8Way, 1 Mux8Way16)
+- [x] `RAM64` (8 RAM8, 1 DMux8Way, 1 Mux8Way16)
+- [x] `RAM512` (8 RAM64, 1 DMux8Way, 1 Mux8Way16)
+- [x] `RAM4K` (8 RAM512, 1 DMux8Way, 1 Mux8Way16)
+- [x] `RAM16K` (8 RAM4K, 1 DMux8Way, 1 Mux8Way16)
+- [x] `PC` (1 Register, 1 Inc16, 1 Or8Way, 1 Mux8Way16)
+
diff --git a/projects/03/a/PC.hdl b/projects/03/a/PC.hdl
index ae8173a..eeee1f1 100644
--- a/projects/03/a/PC.hdl
+++ b/projects/03/a/PC.hdl
@@ -16,5 +16,64 @@ CHIP PC {
     OUT out[16];
 
     PARTS:
-    // Put your code here:
+    // We use this IF inc=1
+    Inc16(in=registerout, out=incrementedoutput);
+
+    // We setup a Mux using the 3 bits as the inputs
+    // for the Mux. Higher priority uses MSB
+    // [ reset | load | inc   ]
+    // [ sel[2]|sel[1]|sel[0] ]
+    // DO NOTHING For this case
+    // a if sel == 000
+    // INC for this case
+    // b if sel == 001
+    // LOAD for the below 2 cases
+    // c if sel == 010
+    // d if sel == 011
+    // RESET for all 4 cases below
+    // e if sel == 100
+    // f if sel == 101
+    // g if sel == 110
+    // h if sel == 111
+    // a-d: we reset
+    // e-f: we load
+    // g: we increment
+    // h: do nothing
+
+    // We don't have a Or3Way, so using this for now
+    // This sets pleaseupdate to true if either of the
+    // reset|load|inc operations is in call
+    Or8Way(
+      in[0]=inc,
+      in[1]=load,
+      in[2]=reset,
+      in[3]=false,
+      in[4]=false,
+      in[5]=false,
+      in[6]=false,
+      in[7]=false,
+      out=pleaseupdate);
+
+    Mux8Way16(
+      // While this is false it doesn't matter
+      // since pleaseupdate = 0 in this case
+      // and register won't reset
+      a=false,
+      // INCREMENT for this case
+      b=incrementedoutput,
+      // LOAD for these 2 cases
+      c=in,
+      d=in,
+      // please pass 0 as input to the register
+      // RESET
+      e=false,
+      f=false,
+      g=false,
+      h=false,
+      sel[2]=reset,
+      sel[1]=load,
+      sel[0]=inc,
+      out=registerinput);
+
+    Register(in=registerinput, load=pleaseupdate, out=registerout, out=out);
 }
diff --git a/projects/03/a/PC.out b/projects/03/a/PC.out
new file mode 100644
index 0000000..5eca76b
--- /dev/null
+++ b/projects/03/a/PC.out
@@ -0,0 +1,31 @@
+| time |   in   |reset|load | inc |  out   |
+| 0+   |      0 |  0  |  0  |  0  |      0 |
+| 1    |      0 |  0  |  0  |  0  |      0 |
+| 1+   |      0 |  0  |  0  |  1  |      0 |
+| 2    |      0 |  0  |  0  |  1  |      1 |
+| 2+   | -32123 |  0  |  0  |  1  |      1 |
+| 3    | -32123 |  0  |  0  |  1  |      2 |
+| 3+   | -32123 |  0  |  1  |  1  |      2 |
+| 4    | -32123 |  0  |  1  |  1  | -32123 |
+| 4+   | -32123 |  0  |  0  |  1  | -32123 |
+| 5    | -32123 |  0  |  0  |  1  | -32122 |
+| 5+   | -32123 |  0  |  0  |  1  | -32122 |
+| 6    | -32123 |  0  |  0  |  1  | -32121 |
+| 6+   |  12345 |  0  |  1  |  0  | -32121 |
+| 7    |  12345 |  0  |  1  |  0  |  12345 |
+| 7+   |  12345 |  1  |  1  |  0  |  12345 |
+| 8    |  12345 |  1  |  1  |  0  |      0 |
+| 8+   |  12345 |  0  |  1  |  1  |      0 |
+| 9    |  12345 |  0  |  1  |  1  |  12345 |
+| 9+   |  12345 |  1  |  1  |  1  |  12345 |
+| 10   |  12345 |  1  |  1  |  1  |      0 |
+| 10+  |  12345 |  0  |  0  |  1  |      0 |
+| 11   |  12345 |  0  |  0  |  1  |      1 |
+| 11+  |  12345 |  1  |  0  |  1  |      1 |
+| 12   |  12345 |  1  |  0  |  1  |      0 |
+| 12+  |      0 |  0  |  1  |  1  |      0 |
+| 13   |      0 |  0  |  1  |  1  |      0 |
+| 13+  |      0 |  0  |  0  |  1  |      0 |
+| 14   |      0 |  0  |  0  |  1  |      1 |
+| 14+  |  22222 |  1  |  0  |  0  |      1 |
+| 15   |  22222 |  1  |  0  |  0  |      0 |