ALU-nostat passing
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@ -32,5 +32,5 @@ Build order as per the website. Cost for each gate in NAND in brackets.
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- [x] FullAdder (2 x HalfAdder, 1 Or)
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- [x] FullAdder (2 x HalfAdder, 1 Or)
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- [x] Add16 (1 x HalfAdder, 15 x FullAdder)
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- [x] Add16 (1 x HalfAdder, 15 x FullAdder)
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- [x] Inc16 (1 x Add16)
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- [x] Inc16 (1 x Add16)
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- [ ] ALU (nostat)
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- [x] ALU (nostat)
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- [ ] ALU (complete)
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- [ ] ALU (complete)
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@ -0,0 +1,37 @@
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| x | y |zx |nx |zy |ny | f |no | out |
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| 0000000000000000 | 1111111111111111 | 1 | 0 | 1 | 0 | 1 | 0 | 0000000000000000 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 1 | 1 | 1 | 1 | 0000000000000001 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 1 | 0 | 1 | 0 | 1111111111111111 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 1 | 1 | 0 | 0 | 0000000000000000 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 0 | 0 | 0 | 0 | 1111111111111111 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 1 | 1 | 0 | 1 | 1111111111111111 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 0 | 0 | 0 | 1 | 0000000000000000 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 1 | 1 | 1 | 1 | 0000000000000000 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 0 | 0 | 1 | 1 | 0000000000000001 |
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| 0000000000000000 | 1111111111111111 | 0 | 1 | 1 | 1 | 1 | 1 | 0000000000000001 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 0 | 1 | 1 | 1 | 0000000000000000 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 1 | 1 | 1 | 0 | 1111111111111111 |
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| 0000000000000000 | 1111111111111111 | 1 | 1 | 0 | 0 | 1 | 0 | 1111111111111110 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 0 | 0 | 1 | 0 | 1111111111111111 |
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| 0000000000000000 | 1111111111111111 | 0 | 1 | 0 | 0 | 1 | 1 | 0000000000000001 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 0 | 1 | 1 | 1 | 1111111111111111 |
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| 0000000000000000 | 1111111111111111 | 0 | 0 | 0 | 0 | 0 | 0 | 0000000000000000 |
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| 0000000000000000 | 1111111111111111 | 0 | 1 | 0 | 1 | 0 | 1 | 1111111111111111 |
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| 0101101110100000 | 0001111011010010 | 1 | 0 | 1 | 0 | 1 | 0 | 0000000000000000 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 1 | 1 | 1 | 1 | 0000000000000001 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 1 | 0 | 1 | 0 | 1111111111111111 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 1 | 1 | 0 | 0 | 0101101110100000 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 0 | 0 | 0 | 0 | 0001111011010010 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 1 | 1 | 0 | 1 | 1010010001011111 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 0 | 0 | 0 | 1 | 1110000100101101 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 1 | 1 | 1 | 1 | 1010010001100000 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 0 | 0 | 1 | 1 | 1110000100101110 |
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| 0101101110100000 | 0001111011010010 | 0 | 1 | 1 | 1 | 1 | 1 | 0101101110100001 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 0 | 1 | 1 | 1 | 0001111011010011 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 1 | 1 | 1 | 0 | 0101101110011111 |
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| 0101101110100000 | 0001111011010010 | 1 | 1 | 0 | 0 | 1 | 0 | 0001111011010001 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 0 | 0 | 1 | 0 | 0111101001110010 |
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| 0101101110100000 | 0001111011010010 | 0 | 1 | 0 | 0 | 1 | 1 | 0011110011001110 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 0 | 1 | 1 | 1 | 1100001100110010 |
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| 0101101110100000 | 0001111011010010 | 0 | 0 | 0 | 0 | 0 | 0 | 0001101010000000 |
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| 0101101110100000 | 0001111011010010 | 0 | 1 | 0 | 1 | 0 | 1 | 0101111111110010 |
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@ -42,5 +42,37 @@ CHIP ALU {
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ng; // 1 if (out < 0), 0 otherwise
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ng; // 1 if (out < 0), 0 otherwise
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PARTS:
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PARTS:
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// Put you code here:
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// if (zx == 1) set x1 = 0
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Mux16(a=x, b=false, sel=zx, out=x1);
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// set x2 = !x1
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Not16(in=x1, out=x2);
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// if (nx == 1), set x3=x2
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Mux16(a=x1, b=x2, sel=nx, out=x3);
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// if (zy == 1) set y1 = 0
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Mux16(a=y, b=false, sel=zy, out=y1);
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// set y2 = !y1
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Not16(in=y1, out=y2);
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// if (ny == 1), set y3=y2
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Mux16(a=y1, b=y2, sel=ny, out=y3);
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// set addition = x3 + y3 (integer 2's complement addition)
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Add16(a=x3, b=y3, out=addition);
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// set andresult = x & y (bitwise and)
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And16(a=x3, b=y3, out=andresult);
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// maybeout == andresult|addition, depending on f(0|1)
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Mux16(a=andresult, b=addition, sel=f, out=maybeout);
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// flippedout = !maybeout
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Not16(in=maybeout, out=flippedout);
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// out = (flippedout|maybeout) depending on no=0|1
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Mux16(a=maybeout, b=flippedout, sel=no, out=out);
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}
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}
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