221 lines
8.0 KiB
Markdown
221 lines
8.0 KiB
Markdown
[Source](http://fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html "Permalink to fpgacpu.org - On FPGAs as PC Coprocessors")
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# fpgacpu.org - On FPGAs as PC Coprocessors
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| ----- |
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| | | | **_On FPGAs as PC Coprocessors_**
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| [**Home][1]**
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[_Regexps in FPGAs][2] **>>**
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**<<** [Emulating FPGAs][3]_
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**Usenet Postings**
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[By Subject][1]
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[By Date][4]**
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**FPGA CPUs**
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[Why FPGA CPUs?][5]
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[Homebuilt processors][6]
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[Altera, Xilinx Announce][7]
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[Soft cores][8]
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[Porting lcc][9]
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[32-bit RISC CPU][10]
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[Superscalar FPGA CPUs][11]
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[Java processors][12]
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[Forth processors][13]
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[Reimplementing Alto][14]
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[Transputers][15]
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[FPGA CPU Speeds][16]
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[Synthesized CPUs][17]
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[Register files][18]
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[Register files (2)][19]
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[Floating point][20]
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[Using block RAM][21]
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[Flex10K CPUs][22]
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[Flex10KE CPUs][23]
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[**Multiprocessors][24]**
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[Multis and fast unis][25]
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[Inner loop datapaths][26]
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[Supercomputers][27]
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**Systems-on-a-Chip**
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[SoC On-Chip Buses][28]
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[On-chip Memory][29]
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[VGA controller][30]
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[Small footprints][31]
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[**CNets][32]**
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[CNets and Datapaths][33]
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[Generators vs. synthesis][34]
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**FPGAs vs. Processors**
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[CPUs vs. FPGAs][35]
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[Emulating FPGAs][3]
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_**FPGAs as coprocessors**_
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[Regexps in FPGAs][2]
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[Life in an FPGA][36]
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[Maximum element][37]
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**Miscellaneous**
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[Floorplanning][38]
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[Pushing on a rope][39]
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[Virtex speculation][40]
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[Rambus for FPGAs][41]
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[3-D rendering][42]
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[LFSR Design][43]
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| [Google][44] SiteSearch
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Newsgroups: comp.arch.fpga
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Subject: On FPGAs as PC coprocessors
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Date: 6 May 1996 22:12:11 GMT
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One of the "way out speculation" questions asked at FCCM 96 (IEEE
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Symposium on FPGAs for Custom Computing Machines) was "when, if ever,
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will an FPGA coprocessor ship on every PC motherboard?"
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Ignoring the daunting language and interface standards issues, and just
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looking at current hardware approaches to FPGA "coprocessors", the
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answer must be "not any time soon".
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Consider that today's power user's CPU (such as a 200 MHz Pentium Pro
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or a 400 MHz Alpha 21164A) *running out of L1 cache* issues peak three
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or four instructions per 2.5-5 ns clock. Also consider that the
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current "low latency high bandwidth" approach to FPGA coprocessor
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integration is to hang the FPGA on the PCI bus.
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In this scenario, the kinds of quasi-general purpose computing problems
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that an FPGA coprocessor can usefully assist with are quite limited.
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Issuing a write and then a read back operation to the FPGA could easily
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take 10 PCI bus cycles (300 ns), assuming no PCI bus contention. In
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that time (assuming hand crafted code (less effort than a FCCM)) a
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Pentium Pro could issue as many as 180 instructions; the Alpha, 480
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64-bit instructions. Future versions of such processors will soon be
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doing VIS- or MMX-like limited bytewise 8+-way SIMD parallelism, and
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eventually superscalar versions of same. Such designs might issue
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between 500 (*) and 4000 (**) hand coded packed byte operations while
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that single 300 ns FPGA write/read is still in progress.
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((At peak speeds like 400e6 clock/s * 4 issue/clock * 8 byte ops/issue,
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e.g. 12e9 byte ops/s, you have to agree that superscalar micros with
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bytewise SIMD are going to displace many FPGA applications on PC and
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workstation platforms.))
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So as long as FPGAs are attached on relatively glacially slow I/O buses
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-- including 32-bit 33 MHz PCI -- it seems unlikely they will be of
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much use in general purpose PC processor acceleration. Sure, for
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applications such as cryptography, image and signal processing, they
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might be a win (***), given a semi-autonomous problem which either fits
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in the FPGA and local storage, or which can employ DMA to stream data
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into or through the FPGA without much CPU intervention or management.
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Of course, the PCI ASIC crowd has the same latency problems, but they
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dont share FCCM aspirations of accelerating general purpose computing,
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rather they focus on the same aforementioned special purpose
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applications.
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Five times better latency and four times better bandwidth could be
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achieved if FPGA vendors invent a way to directly connect their parts
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to the Pentium Pro external bus, as a peer of the memory/bus
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controller. A custom, dedicated Pentium Pro interface would probably
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be required, since FPGA configurable logic would be too slow and
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electrically incompatible.
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This could be a good volume business, and not quite the moving target
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it might appear -- I expect the PPro external bus to be just as
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ubiquitous and as long lived as have been the 486 and Pentium buses.
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Someone could make a plug in card which sits in the PPro ZIF socket and
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which hosts a PPro and its FPGA(s).
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Alternately, the FPGA coprocessor could be attached on the new advanced
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graphics memory port, or whatever it is to be called, that will be
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available in future Intel memory/PCI controller chipsets.
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One might argue that Xilinx made a big mistake in not offering a
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version of the XC6200 with a dedicated 66 MHz Pentium external bus
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interface -- after all it is by far the most popular and most supported
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processor interface for the most lucrative general computing market.
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If any vendor does pursue this idea, I would appreciate a couple of
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sample parts. :-)
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--
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(*) 500 op in 300 ns: forthcoming 200 MHz PPro with MMX: 60 clocks x 1
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8-byte MMX insn/clock
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(**) 4000 op in 300 ns: hypothetical 400 MHz Alpha with each integer
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unit enhanced for bytewise SIMD: 120 clocks x 4 8-byte insns/clock
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(***) "win": much cheaper/faster than simply adding a second processor
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--
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Acknowledgements: this posting is a spin-off of a discussion with Mark
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Shand, and the "way out speculative" question was suggested by Mike
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Butts.
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Jan Gray
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Copyright © 2000, Gray Research LLC. All rights reserved.
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Last updated: Feb 03 2001
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[1]: http://fpgacpu.org/index.html
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[2]: http://fpgacpu.org/re.html
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[3]: http://fpgacpu.org/emulating_fpgas.html
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[4]: http://fpgacpu.org/bydate.html
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[5]: http://fpgacpu.org/why.html
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[6]: http://fpgacpu.org/homebrew.html
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[7]: http://fpgacpu.org/a-x-announce.html
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[8]: http://fpgacpu.org/soft.html
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[9]: http://fpgacpu.org/lcc.html
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[10]: http://fpgacpu.org/32bits.html
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[11]: http://fpgacpu.org/superscalar.html
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[12]: http://fpgacpu.org/javaproc.html
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[13]: http://fpgacpu.org/forth.html
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[14]: http://fpgacpu.org/alto.html
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[15]: http://fpgacpu.org/transputer.html
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[16]: http://fpgacpu.org/speed.html
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[17]: http://fpgacpu.org/synth_cpu.html
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[18]: http://fpgacpu.org/regfile.html
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[19]: http://fpgacpu.org/regfile2.html
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[20]: http://fpgacpu.org/fp.html
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[21]: http://fpgacpu.org/bb.html
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[22]: http://fpgacpu.org/altera_cpus.html
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[23]: http://fpgacpu.org/altera_cpus_dual_port_EABs.html
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[24]: http://fpgacpu.org/multiprocessors.html
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[25]: http://fpgacpu.org/multis_and_fast_fpgacpus.html
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[26]: http://fpgacpu.org/innerloop.html
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[27]: http://fpgacpu.org/array.html
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[28]: http://fpgacpu.org/buses.html
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[29]: http://fpgacpu.org/memory.html
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[30]: http://fpgacpu.org/vga.html
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[31]: http://fpgacpu.org/12mm2.html
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[32]: http://fpgacpu.org/cnets.html
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[33]: http://fpgacpu.org/cnets_datapath.html
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[34]: http://fpgacpu.org/generators.html
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[35]: http://fpgacpu.org/cpus_vs_fpgas.html
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[36]: http://fpgacpu.org/life.html
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[37]: http://fpgacpu.org/max.html
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[38]: http://fpgacpu.org/floorplanning.html
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[39]: http://fpgacpu.org/rope_pushing.html
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[40]: http://fpgacpu.org/virtex_spec.html
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[41]: http://fpgacpu.org/rambus.html
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[42]: http://fpgacpu.org/render.html
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[43]: http://fpgacpu.org/lfsrs.html
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[44]: http://www.google.com
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