52 lines
1.5 KiB
Plaintext
52 lines
1.5 KiB
Plaintext
// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/b/RAM4K.hdl
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/**
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* Memory of 4K registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM4K {
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IN in[16], load, address[12];
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OUT out[16];
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PARTS:
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// The MSB of the address picks which RAM512 module is being picked
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DMux8Way(in=load, sel=address[9..11],
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a=load1,
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b=load2,
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c=load3,
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d=load4,
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e=load5,
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f=load6,
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g=load7,
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h=load8);
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// We use the LSB of the address to pick the register inside the RAM512
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RAM512(in=in, load=load1, address=address[0..8], out=out1);
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RAM512(in=in, load=load2, address=address[0..8], out=out2);
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RAM512(in=in, load=load3, address=address[0..8], out=out3);
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RAM512(in=in, load=load4, address=address[0..8], out=out4);
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RAM512(in=in, load=load5, address=address[0..8], out=out5);
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RAM512(in=in, load=load6, address=address[0..8], out=out6);
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RAM512(in=in, load=load7, address=address[0..8], out=out7);
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RAM512(in=in, load=load8, address=address[0..8], out=out8);
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// MSB
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Mux8Way16(
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a=out1,
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b=out2,
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c=out3,
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d=out4,
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e=out5,
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f=out6,
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g=out7,
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h=out8,
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sel=address[9..11], out=out);
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}
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