// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl

/**
 * Memory of 16K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];

    PARTS:
    // The MSB of the address picks which RAM4K module is being picked
    DMux4Way(in=load, sel=address[12..13],
      a=load1,
      b=load2,
      c=load3,
      d=load4
    );

    // We use the LSB of the address to pick the register inside the RAM4K
    RAM4K(in=in, load=load1, address=address[0..11], out=out1);
    RAM4K(in=in, load=load2, address=address[0..11], out=out2);
    RAM4K(in=in, load=load3, address=address[0..11], out=out3);
    RAM4K(in=in, load=load4, address=address[0..11], out=out4);

    // MSB
    Mux4Way16(
      a=out1,
      b=out2,
      c=out3,
      d=out4,
      sel=address[12..13], out=out);
}