// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:

    // The MSB of the address picks which RAM512 module is being picked
    DMux8Way(in=load, sel=address[9..11],
      a=load1,
      b=load2,
      c=load3,
      d=load4,
      e=load5,
      f=load6,
      g=load7,
      h=load8);

    // We use the LSB of the address to pick the register inside the RAM512
    RAM512(in=in, load=load1, address=address[0..8], out=out1);
    RAM512(in=in, load=load2, address=address[0..8], out=out2);
    RAM512(in=in, load=load3, address=address[0..8], out=out3);
    RAM512(in=in, load=load4, address=address[0..8], out=out4);
    RAM512(in=in, load=load5, address=address[0..8], out=out5);
    RAM512(in=in, load=load6, address=address[0..8], out=out6);
    RAM512(in=in, load=load7, address=address[0..8], out=out7);
    RAM512(in=in, load=load8, address=address[0..8], out=out8);

    // MSB
    Mux8Way16(
      a=out1,
      b=out2,
      c=out3,
      d=out4,
      e=out5,
      f=out6,
      g=out7,
      h=out8,
      sel=address[9..11], out=out);
}