[05/CPU] Implements most of the CPU
This includes: - Handling of data i/o (for A/D/M) - Handling the ALU properly (all 28 computations) - Basic incremental PC (i/o) - PC reset - read/write to M What's missing: - Handling jumps
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@ -6,23 +6,23 @@
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/**
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* The Hack CPU (Central Processing unit), consisting of an ALU,
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* two registers named A and D, and a program counter named PC.
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* The CPU is designed to fetch and execute instructions written in
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* The CPU is designed to fetch and execute instructions written in
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* the Hack machine language. In particular, functions as follows:
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* Executes the inputted instruction according to the Hack machine
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* Executes the inputted instruction according to the Hack machine
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* language specification. The D and A in the language specification
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* refer to CPU-resident registers, while M refers to the external
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* memory location addressed by A, i.e. to Memory[A]. The inM input
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* holds the value of this location. If the current instruction needs
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* to write a value to M, the value is placed in outM, the address
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* of the target location is placed in the addressM output, and the
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* writeM control bit is asserted. (When writeM==0, any value may
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* appear in outM). The outM and writeM outputs are combinational:
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* they are affected instantaneously by the execution of the current
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* instruction. The addressM and pc outputs are clocked: although they
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* are affected by the execution of the current instruction, they commit
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* to their new values only in the next time step. If reset==1 then the
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* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
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* than to the address resulting from executing the current instruction.
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* memory location addressed by A, i.e. to Memory[A]. The inM input
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* holds the value of this location. If the current instruction needs
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* to write a value to M, the value is placed in outM, the address
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* of the target location is placed in the addressM output, and the
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* writeM control bit is asserted. (When writeM==0, any value may
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* appear in outM). The outM and writeM outputs are combinational:
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* they are affected instantaneously by the execution of the current
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* instruction. The addressM and pc outputs are clocked: although they
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* are affected by the execution of the current instruction, they commit
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* to their new values only in the next time step. If reset==1 then the
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* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
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* than to the address resulting from executing the current instruction.
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*/
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CHIP CPU {
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@ -34,10 +34,85 @@ CHIP CPU {
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// the current program (reset==0).
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OUT outM[16], // M value output
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writeM, // Write to M?
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writeM, // Write to M?
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addressM[15], // Address in data memory (of M)
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pc[15]; // address of next instruction
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PARTS:
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// Put your code here:
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}
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// instructions[15] = instructionC
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// Specifically, when C instruction
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// instruction[14] = 1
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// instruction[13] = 1
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// instruction[12] = a
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// instruction[11] = c1
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// instruction[10] = c2
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// instruction[9] = c3
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// instruction[8] = c4
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// instruction[7] = c5
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// instruction[6] = c6
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// instruction[5] = d1
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// instruction[4] = d2
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// instruction[3] = d3
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// instruction[2] = j1
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// instruction[1] = j2
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// instruction[0] = j3
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// we write to A based on the following truth table
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// i[15] = true = instruction =C
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// i[5] = true = d1 = true = write ALU output to register A
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// i[15] | i[5] | write?| t1
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// 0 | 0 | 1 | 1
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// 0 | 1 | 1 | 1
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// 1 | 0 | 0 | 1
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// 1 | 1 | 1 | 0
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Nand(a=instruction[15], b=instruction[5], out=t1);
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Nand(a=t1, b=instruction[15], out=writeA);
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// But the input to registerA is picked b/w instruction[0..14] | aluoutput
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// depending on instructionA
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// registerAInput = {
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// [0, instruction[0..14]] if instruction[15] = 0
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// aluoutput if instruction[15] = 1
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// }
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Mux16(a[15]=false,
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a[0..14]=instruction[0..14],
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b=aluoutput,
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sel=instruction[15],
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out=registerAInput);
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// Register A
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ARegister(in=registerAInput,
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load=writeA,
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out=registerA, out[0..14]=addressM);
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// Register D (instruction[4] = d2)
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DRegister(in=aluoutput, load=instruction[4], out=registerD);
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// TODO: support jumps
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PC(in=registerA, load=false, inc=true, reset=reset, out[0..14]=pc);
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// the "a" bit = instruction[12] decides whether Y = registerA | inM
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Mux16(a=registerA, b=inM, sel=instruction[12], out=y);
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ALU(x=registerD,
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y=y,
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// control bits start
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zx=instruction[11],
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nx=instruction[10],
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zy=instruction[9],
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ny=instruction[8],
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f=instruction[7],
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no=instruction[6],
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// control bits end
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out=aluoutput,
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out=outM,
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zr=zr, ng=ng);
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// if we are on instruction C, and d3 is true
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And(a=instruction[3], b=instruction[15], out=writeM);
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}
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@ -0,0 +1,25 @@
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|time| inM | instruction |reset| outM |writeM |addre| pc |DRegiste|
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|0+ | 0|0011000000111001| 0 | 0| 0 | 0| 0| 0 |
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|1 | 0|0011000000111001| 0 | 0| 0 |12345| 1| 0 |
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|1+ | 0|1110110000010000| 0 | 12345| 0 |12345| 1| 12345 |
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|2 | 0|1110110000010000| 0 | 12345| 0 |12345| 2| 12345 |
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|2+ | 0|0101101110100000| 0 | -1| 0 |12345| 2| 12345 |
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|3 | 0|0101101110100000| 0 | -1| 0 |23456| 3| 12345 |
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|3+ | 0|1110000111010000| 0 | 11111| 0 |23456| 3| 11111 |
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|4 | 0|1110000111010000| 0 | 12345| 0 |23456| 4| 11111 |
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|4+ | 0|0000001111101000| 0 | -11111| 0 |23456| 4| 11111 |
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|5 | 0|0000001111101000| 0 | -11111| 0 | 1000| 5| 11111 |
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|5+ | 0|1110001100001000| 0 | 11111| 1 | 1000| 5| 11111 |
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|6 | 0|1110001100001000| 0 | 11111| 1 | 1000| 6| 11111 |
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|6+ | 0|0000001111101001| 0 | -11111| 0 | 1000| 6| 11111 |
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|7 | 0|0000001111101001| 0 | -11111| 0 | 1001| 7| 11111 |
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|7+ | 0|1110001110011000| 0 | 11110| 1 | 1001| 7| 11110 |
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|8 | 0|1110001110011000| 0 | 11109| 1 | 1001| 8| 11110 |
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|8+ | 0|0000001111101000| 0 | -11110| 0 | 1001| 8| 11110 |
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|9 | 0|0000001111101000| 0 | -11110| 0 | 1000| 9| 11110 |
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|9+ | 11111|1111010011010000| 0 | -1| 0 | 1000| 9| -1 |
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|10 | 11111|1111010011010000| 0 | -11112| 0 | 1000| 10| -1 |
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|10+ | 11111|0000000000001110| 0 | 1000| 0 | 1000| 10| -1 |
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|11 | 11111|0000000000001110| 0 | 14| 0 | 14| 11| -1 |
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|11+ | 11111|1110001100000100| 0 | -1| 0 | 14| 11| -1 |
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|12 | 11111|1110001100000100| 0 | -1| 0 | 14| 12| -1 |
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