From 93d6273201ed012e074cc85787688774342102cb Mon Sep 17 00:00:00 2001 From: Nemo Date: Wed, 20 May 2020 19:13:01 +0530 Subject: [PATCH] [03] RAM8 --- README.md | 2 +- projects/03/a/RAM8.hdl | 43 +++++++++- projects/03/a/RAM8.out | 173 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 213 insertions(+), 5 deletions(-) create mode 100644 projects/03/a/RAM8.out diff --git a/README.md b/README.md index deb23a2..d044e94 100644 --- a/README.md +++ b/README.md @@ -42,7 +42,7 @@ Make sure you read through the [Hardware Simulator Tutorial](https://b1391bd6-da - [x] DFF (primitive) - [x] Bit (1 Mux, 1DFF) - [x] Register (16 Bits) -- [ ] RAM8 +- [x] RAM8 (8 Registers, 1 DMux8Way, 1 Mux8Way16) - [ ] RAM64 - [ ] RAM512 - [ ] RAM4K diff --git a/projects/03/a/RAM8.hdl b/projects/03/a/RAM8.hdl index efa885d..e36677a 100644 --- a/projects/03/a/RAM8.hdl +++ b/projects/03/a/RAM8.hdl @@ -5,8 +5,8 @@ /** * Memory of 8 registers, each 16 bit-wide. Out holds the value - * stored at the memory location specified by address. If load==1, then - * the in value is loaded into the memory location specified by address + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address * (the loaded value will be emitted to out from the next time step onward). */ @@ -15,5 +15,40 @@ CHIP RAM8 { OUT out[16]; PARTS: - // Put your code here: -} \ No newline at end of file + // All our registers can just use + // the same input signal + // but pick the load from different places + Register(in=in, load=load1, out=out1); + Register(in=in, load=load2, out=out2); + Register(in=in, load=load3, out=out3); + Register(in=in, load=load4, out=out4); + Register(in=in, load=load5, out=out5); + Register(in=in, load=load6, out=out6); + Register(in=in, load=load7, out=out7); + Register(in=in, load=load8, out=out8); + + // We take our load signal, DMux it to 8 signals + // deciding by the address passed to us + DMux8Way(in=load, sel=address, + a=load1, + b=load2, + c=load3, + d=load4, + e=load5, + f=load6, + g=load7, + h=load8); + + // Take the output of all the registers + // and return based on the address + Mux8Way16( + a=out1, + b=out2, + c=out3, + d=out4, + e=out5, + f=out6, + g=out7, + h=out8, + sel=address, out=out); +} diff --git a/projects/03/a/RAM8.out b/projects/03/a/RAM8.out new file mode 100644 index 0000000..68df551 --- /dev/null +++ b/projects/03/a/RAM8.out @@ -0,0 +1,173 @@ +| time | in |load |address| out | +| 0+ | 0 | 0 | 0 | 0 | +| 1 | 0 | 0 | 0 | 0 | +| 1+ | 0 | 1 | 0 | 0 | +| 2 | 0 | 1 | 0 | 0 | +| 2+ | 11111 | 0 | 0 | 0 | +| 3 | 11111 | 0 | 0 | 0 | +| 3+ | 11111 | 1 | 1 | 0 | +| 4 | 11111 | 1 | 1 | 11111 | +| 4+ | 11111 | 0 | 0 | 0 | +| 5 | 11111 | 0 | 0 | 0 | +| 5+ | 3333 | 0 | 3 | 0 | +| 6 | 3333 | 0 | 3 | 0 | +| 6+ | 3333 | 1 | 3 | 0 | +| 7 | 3333 | 1 | 3 | 3333 | +| 7+ | 3333 | 0 | 3 | 3333 | +| 8 | 3333 | 0 | 3 | 3333 | +| 8 | 3333 | 0 | 1 | 11111 | +| 8+ | 7777 | 0 | 1 | 11111 | +| 9 | 7777 | 0 | 1 | 11111 | +| 9+ | 7777 | 1 | 7 | 0 | +| 10 | 7777 | 1 | 7 | 7777 | +| 10+ | 7777 | 0 | 7 | 7777 | +| 11 | 7777 | 0 | 7 | 7777 | +| 11 | 7777 | 0 | 3 | 3333 | +| 11 | 7777 | 0 | 7 | 7777 | +| 11+ | 7777 | 0 | 0 | 0 | +| 12 | 7777 | 0 | 0 | 0 | +| 12 | 7777 | 0 | 1 | 11111 | +| 12 | 7777 | 0 | 2 | 0 | +| 12 | 7777 | 0 | 3 | 3333 | +| 12 | 7777 | 0 | 4 | 0 | +| 12 | 7777 | 0 | 5 | 0 | +| 12 | 7777 | 0 | 6 | 0 | +| 12 | 7777 | 0 | 7 | 7777 | +| 12+ | 21845 | 1 | 0 | 0 | +| 13 | 21845 | 1 | 0 | 21845 | +| 13+ | 21845 | 1 | 1 | 11111 | +| 14 | 21845 | 1 | 1 | 21845 | +| 14+ | 21845 | 1 | 2 | 0 | +| 15 | 21845 | 1 | 2 | 21845 | +| 15+ | 21845 | 1 | 3 | 3333 | +| 16 | 21845 | 1 | 3 | 21845 | +| 16+ | 21845 | 1 | 4 | 0 | +| 17 | 21845 | 1 | 4 | 21845 | +| 17+ | 21845 | 1 | 5 | 0 | +| 18 | 21845 | 1 | 5 | 21845 | +| 18+ | 21845 | 1 | 6 | 0 | +| 19 | 21845 | 1 | 6 | 21845 | +| 19+ | 21845 | 1 | 7 | 7777 | +| 20 | 21845 | 1 | 7 | 21845 | +| 20+ | 21845 | 0 | 0 | 21845 | +| 21 | 21845 | 0 | 0 | 21845 | +| 21 | 21845 | 0 | 1 | 21845 | +| 21 | 21845 | 0 | 2 | 21845 | +| 21 | 21845 | 0 | 3 | 21845 | +| 21 | 21845 | 0 | 4 | 21845 | +| 21 | 21845 | 0 | 5 | 21845 | +| 21 | 21845 | 0 | 6 | 21845 | +| 21 | 21845 | 0 | 7 | 21845 | +| 21+ | -21846 | 1 | 0 | 21845 | +| 22 | -21846 | 1 | 0 | -21846 | +| 22+ | -21846 | 0 | 0 | -21846 | +| 23 | -21846 | 0 | 0 | -21846 | +| 23 | -21846 | 0 | 1 | 21845 | +| 23 | -21846 | 0 | 2 | 21845 | +| 23 | -21846 | 0 | 3 | 21845 | +| 23 | -21846 | 0 | 4 | 21845 | +| 23 | -21846 | 0 | 5 | 21845 | +| 23 | -21846 | 0 | 6 | 21845 | +| 23 | -21846 | 0 | 7 | 21845 | +| 23+ | 21845 | 1 | 0 | -21846 | +| 24 | 21845 | 1 | 0 | 21845 | +| 24+ | -21846 | 1 | 1 | 21845 | +| 25 | -21846 | 1 | 1 | -21846 | +| 25+ | -21846 | 0 | 0 | 21845 | +| 26 | -21846 | 0 | 0 | 21845 | +| 26 | -21846 | 0 | 1 | -21846 | +| 26 | -21846 | 0 | 2 | 21845 | +| 26 | -21846 | 0 | 3 | 21845 | +| 26 | -21846 | 0 | 4 | 21845 | +| 26 | -21846 | 0 | 5 | 21845 | +| 26 | -21846 | 0 | 6 | 21845 | +| 26 | -21846 | 0 | 7 | 21845 | +| 26+ | 21845 | 1 | 1 | -21846 | +| 27 | 21845 | 1 | 1 | 21845 | +| 27+ | -21846 | 1 | 2 | 21845 | +| 28 | -21846 | 1 | 2 | -21846 | +| 28+ | -21846 | 0 | 0 | 21845 | +| 29 | -21846 | 0 | 0 | 21845 | +| 29 | -21846 | 0 | 1 | 21845 | +| 29 | -21846 | 0 | 2 | -21846 | +| 29 | -21846 | 0 | 3 | 21845 | +| 29 | -21846 | 0 | 4 | 21845 | +| 29 | -21846 | 0 | 5 | 21845 | +| 29 | -21846 | 0 | 6 | 21845 | +| 29 | -21846 | 0 | 7 | 21845 | +| 29+ | 21845 | 1 | 2 | -21846 | +| 30 | 21845 | 1 | 2 | 21845 | +| 30+ | -21846 | 1 | 3 | 21845 | +| 31 | -21846 | 1 | 3 | -21846 | +| 31+ | -21846 | 0 | 0 | 21845 | +| 32 | -21846 | 0 | 0 | 21845 | +| 32 | -21846 | 0 | 1 | 21845 | +| 32 | -21846 | 0 | 2 | 21845 | +| 32 | -21846 | 0 | 3 | -21846 | +| 32 | -21846 | 0 | 4 | 21845 | +| 32 | -21846 | 0 | 5 | 21845 | +| 32 | -21846 | 0 | 6 | 21845 | +| 32 | -21846 | 0 | 7 | 21845 | +| 32+ | 21845 | 1 | 3 | -21846 | +| 33 | 21845 | 1 | 3 | 21845 | +| 33+ | -21846 | 1 | 4 | 21845 | +| 34 | -21846 | 1 | 4 | -21846 | +| 34+ | -21846 | 0 | 0 | 21845 | +| 35 | -21846 | 0 | 0 | 21845 | +| 35 | -21846 | 0 | 1 | 21845 | +| 35 | -21846 | 0 | 2 | 21845 | +| 35 | -21846 | 0 | 3 | 21845 | +| 35 | -21846 | 0 | 4 | -21846 | +| 35 | -21846 | 0 | 5 | 21845 | +| 35 | -21846 | 0 | 6 | 21845 | +| 35 | -21846 | 0 | 7 | 21845 | +| 35+ | 21845 | 1 | 4 | -21846 | +| 36 | 21845 | 1 | 4 | 21845 | +| 36+ | -21846 | 1 | 5 | 21845 | +| 37 | -21846 | 1 | 5 | -21846 | +| 37+ | -21846 | 0 | 0 | 21845 | +| 38 | -21846 | 0 | 0 | 21845 | +| 38 | -21846 | 0 | 1 | 21845 | +| 38 | -21846 | 0 | 2 | 21845 | +| 38 | -21846 | 0 | 3 | 21845 | +| 38 | -21846 | 0 | 4 | 21845 | +| 38 | -21846 | 0 | 5 | -21846 | +| 38 | -21846 | 0 | 6 | 21845 | +| 38 | -21846 | 0 | 7 | 21845 | +| 38+ | 21845 | 1 | 5 | -21846 | +| 39 | 21845 | 1 | 5 | 21845 | +| 39+ | -21846 | 1 | 6 | 21845 | +| 40 | -21846 | 1 | 6 | -21846 | +| 40+ | -21846 | 0 | 0 | 21845 | +| 41 | -21846 | 0 | 0 | 21845 | +| 41 | -21846 | 0 | 1 | 21845 | +| 41 | -21846 | 0 | 2 | 21845 | +| 41 | -21846 | 0 | 3 | 21845 | +| 41 | -21846 | 0 | 4 | 21845 | +| 41 | -21846 | 0 | 5 | 21845 | +| 41 | -21846 | 0 | 6 | -21846 | +| 41 | -21846 | 0 | 7 | 21845 | +| 41+ | 21845 | 1 | 6 | -21846 | +| 42 | 21845 | 1 | 6 | 21845 | +| 42+ | -21846 | 1 | 7 | 21845 | +| 43 | -21846 | 1 | 7 | -21846 | +| 43+ | -21846 | 0 | 0 | 21845 | +| 44 | -21846 | 0 | 0 | 21845 | +| 44 | -21846 | 0 | 1 | 21845 | +| 44 | -21846 | 0 | 2 | 21845 | +| 44 | -21846 | 0 | 3 | 21845 | +| 44 | -21846 | 0 | 4 | 21845 | +| 44 | -21846 | 0 | 5 | 21845 | +| 44 | -21846 | 0 | 6 | 21845 | +| 44 | -21846 | 0 | 7 | -21846 | +| 44+ | 21845 | 1 | 7 | -21846 | +| 45 | 21845 | 1 | 7 | 21845 | +| 45+ | 21845 | 0 | 0 | 21845 | +| 46 | 21845 | 0 | 0 | 21845 | +| 46 | 21845 | 0 | 1 | 21845 | +| 46 | 21845 | 0 | 2 | 21845 | +| 46 | 21845 | 0 | 3 | 21845 | +| 46 | 21845 | 0 | 4 | 21845 | +| 46 | 21845 | 0 | 5 | 21845 | +| 46 | 21845 | 0 | 6 | 21845 | +| 46 | 21845 | 0 | 7 | 21845 |