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34 KiB
Markdown
5 lines
34 KiB
Markdown
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[Source](http://www.dabo.de/ccc99/www.camp.ccc.de/radio/help.txt "Permalink to ")
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From: mark@omnifest.uwm.edu (Mark Hopkins) Newsgroups: alt.lang.asm Subject: A Summary of the 80486 Opcodes and Instructions (1) The 80x86 is an Octal Machine This is a follow-up and revision of an article posted in alt.lang.asm on 7-5-92 concerning the 80x86 instruction encoding. Some bugs were corrected June, the 20th, 1997 by S.Klose (sven@devcon.net) (minor bugs in 32bit effective addresses and opcode typoes) The only proper way to understand 80x86 coding is to realize that ALL 80x86 OPCODES ARE CODED IN OCTAL. A byte has 3 octal digits, ranging from 000 to 377\. In fact, each octal group (000-077, 100-177, etc.) tends to encode a specific variety of operation. All of these are features inherited from the 8080/8085/Z80. For some reason absolutely everybody misses all of this, even the Intel people who wrote the reference on the 8086 (and even the 8080). The opcode scheme outlined briefly below is expanded starting in the 80386, but consistently with the overall scheme here. As an example to see how this works, the mov instructions in octal are: 210 xrm mov Eb, Rb 211 xrm mov Ew, Rw 212 xrm mov Rb, Eb 213 xrm mov Rw, Ew 214 xsm mov Ew, SR 216 xsm mov SR, Ew The meanings of the octal digits (x, m, r, s) and their correspondence to the operands (Eb, Ew, Rb, Rw, SR) are the following: The digit r (0-7) encodes the register operand as follows: REGISTER (r): 0 1 2 3 4 5 6 7 Rb = Byte-sized register AL CL DL BL AH CH DL BH Rw = Word-sized register AX CX DX BX SP BP SI DI The segment register digit s (0-7) encodes the segment register as follows: SEGMENT REGISTER (s): 0 1 2 3 4 5 6 7 SR = Segment register ES CS SS DS The digits x (0-3), and m (0-7) encode the address mode according to the following scheme. One or more bytes (labeled: Disp) may immediately follow xrm as described below. TABLE 1: 16-BIT ADDRESSING MODE (x, m): Eb = Address of byte-sized object in memory or register Ew = Address of word-sized object in memory or register Dw = Unsigned word Dc = Signed byte ("character"), range: -128 to +127 (decimal). Db = Unsigned byte x m Disp Eb Ew \------------------ 3 r Rb Rw 0 6 Dw DS:[Dw] 0 m Base:[0] (except for xm = 06). 1 m Dc Base:[Dc] 2 m Dw Base:[Dw] x 0 Disp DS:[BX + SI + Disp] x 1 Disp DS:[BX + DI + Disp] x 2 Disp SS:[BP + SI + Disp] x 3 Disp SS:[BP + DI + Disp] x 4 Disp DS:[SI + Disp] x 5 Disp SS:[DI + Disp] x 6 Disp DS:[BP + Disp] (except for xm = 06) x 7 Disp DS:[BX + Disp] This expands into the following table: TABLE 1a: 16-BIT ADDRESSING MODE (x, m) for the expansion impaired. :) xm Eb/Ew xm Eb/Ew xm Eb/Ew xm Eb/Ew 00 DS:[BX + SI] 10 Dc DS:[BX + SI + Dc] 20 Dw DS:[BX + SI + Dw] 30 AL/AX 01 DS:[BX + DI] 11 Dc DS:[BX + DI + Dc] 21 Dw DS:[BX + DI + Dw] 31 CL/CX 02 SS:[BX + SI] 12 Dc SS:[BP + SI + Dc] 22 Dw SS:[BP + SI + Dw] 32 DL/DX 03 SS:[BX + DI] 13 Dc SS:[BP + DI + Dc] 23 Dw SS:[BP + DI + Dw] 33 BL/BX 04 DS:[SI] 14 Dc DS:[SI + Dc] 24 Dw DS:[SI + Dw] 34 AH/SP 05 DS:[DI] 15 Dc DS:[DI + Dc] 25 Dw DS:[DI + Dw] 35 CH/BP 06 Dw DS:[Dw] 16 Dc SS:[BP + Dc] 26 Dw SS:[BP + Dw] 36 DH/SI 07 DS:[BX] 17 Dc DS:[BX + Dc] 27 Dw DS:[BX + Dw] 37 BH/DI Operands where x is 0, 1, or 2 are all pointers. If the instruction is a WORD instruction (211, 213, 214, 216 are), then this pointer addresses a word-sized object. The format of the object at the indicated address will always be low-order byte first, and high-order byte second. Otherwise the instruction is a BYTE instruction (210, 212) and the pointer addresses byte-sized object at the indicated address. The default segments (DS:, SS:) can be overridden with a segment prefix. In all cases it's understood that everything has the default segment DS, except for the two stack/frame pointers (BP and SP) whose default segment is SS. That will be explained below. Modes where x = 1, or 2 will require displacement bytes (Dc or Dw) to follow the opcode as explained above. When x = 3, WORD sized instructions address the word registers (AX, CX, ...) and the BYTE size instructions the byte registers (AL, CL, ...). EXAMPLE 1: The instruction opcode: 210 135 375 Here, xm = 15, and r = 3, so t
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