hn-classics/_stories/1996/10612358.md

---
created_at: '2015-11-23T01:32:05.000Z'
title: Caltech Potato Chips (1996)
url: http://www.async.caltech.edu/~mika/potato/potato.html
author: ch
points: 46
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[Source](http://www.async.caltech.edu/~mika/potato/potato.html "Permalink to Potato Chips")

# Potato Chips

# Caltech Potato Chips

[ ![ ][1]][2] [ ![ ][3]][4] [ ![ ][5]][6] ![ ][7]   
  
Have you ever seen a RISC processor run off the power of a potato before? I bet you haven't! This is the story of the world's possibly first and only vegetable-powered RISC processor. 

The [Caltech Asynchronous Microprocessor][2] was designed by the [Asynchronous VLSI group][8] in 1988 and 1989 and manufactured through [MOSIS][9] in 2.0 micron (and later 1.6 micron) two-level-metal CMOS, a state-of-the art technology in the mid-to-late eighties. (By comparison, today's (January 1996) state-of-the art technologies have feature sizes of about 0.25 microns. Consequently, modern CMOS circuits are about fifty times denser, run twenty times faster, and consume considerably less power than their 1980's predecessors.) 

[(Continued...)][10]   
  
_By [Mika Nystr&oumlm;][11], [mika@vlsi.cs.caltech.edu][12] January 16, 1996._

[1]: http://www.cs.caltech.edu/pictures/uP3.gif
[2]: http://www.cs.caltech.edu/pictures/uP.gif
[3]: http://www.async.caltech.edu/cpu-small.jpg
[4]: http://www.async.caltech.edu/cpu.jpg
[5]: http://www.async.caltech.edu/mpotato-small.jpg
[6]: http://www.async.caltech.edu/mpotato.jpg
[7]: http://www.async.caltech.edu/POTATO-small.jpg
[8]: http://www.cs.caltech.edu/~alains
[9]: http://www.isi.edu:80/mosis/
[10]: http://www.async.caltech.edu/potato2.html
[11]: http://www.cs.caltech.edu/~mika/
[12]: mailto:mika%40vlsi.cs.caltech.edu